View STMPE812_7766552.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. july 2010 doc id 17732 rev 1 1/49 49 STMPE812 enhanced 4-wire resistive touc hscreen controller with pwm features 4 gpios (8 ma drive, 12 ma sink at 3.3 v) 1 additional, general purpose 12-bit adc operating voltage 1.65 - 3.6 v integrated 4-wire touchscreen controller, pen- down/real-time mode, fully-autonomous 1 pwm controller auto-hibernation and low power ? typ 0.5 a in hibernation mode ? typ 100 a in active mode interrupt output pin (optional) reset input pin (optional) wake-up feature on each port configured as gpio input i 2 c interface 8 kv hbm, 1 kv cdm esd protection on x+/x-/y+/y- 2 kv hbm, 250 v cdm esd protection on all other pins applications portable media players game consoles mobile and smart phones description the STMPE812 is a 4-wire resistive touchscreen controller with 4-bit port expander integrated. the touchscreen controller is designed to be fully autonomous, requiring only minimal cpu intervention for sampling, filtering and pre- processing operations. flip-chip 12 (2.17 x 1.67 mm) table 1. device summary order code package packaging STMPE812bjr flip-chip 12 (2.17 x 1.67 mm) tape and reel www.st.com
contents STMPE812 2/49 doc id 17732 rev 1 contents 1 STMPE812 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 i 2 c features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 STMPE812 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 auto-increment/non auto-increment address . . . . . . . . . . . . . . . . . . . . . . 16 7 system and identificati on registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 adc controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1 register map for pwm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.2 interrupt of pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11 touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.1 touchscreen controller detection sequence . . . . . . . . . . . . . . . . . . . . . . . 30 11.2 3 modes of acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.3 touchscreen controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.4 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STMPE812 contents doc id 17732 rev 1 3/49 12 gpio port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.2 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 14 package mechanical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STMPE812 functional overview STMPE812 4/49 doc id 17732 rev 1 1 STMPE812 functional overview the STMPE812 consists of the following blocks: i 2 c interface gpio/pwm controller touchscreen controller (tsc) analog-to-digital converted (adc) driver and switch control unit figure 1. block diagram !-6 vdd scl sda gnd gpio0/adc/pwm1 i2c interface i2c interface power management power management reset system por reset system por por tou ch screen drivers and switches tou ch screen drivers and switches gpio/pwm controller gpio/pwm controller m u x adc tsc adc adc tsc tsc y- y+ x- x+ y- y+ x- x+ gpio1/adc gpio2/reset gpio3/int tsc: touchscreen controller adc: analog to digital converter
STMPE812 STMPE812 fu nctional overview doc id 17732 rev 1 5/49 1.1 pin configuration and functions figure 2. pin configuration (top through view) table 2. pin assignments pin name current capacity function b3 y+ 50 ma current limit y+ c3 x- 50 ma current limit x- d3 y- 50 ma current limit y- c2 p1 +8 ma/-12 ma at 3.3 v gpio-0 / adc / pwm1 (3.6 v tolerant within v cc valid range) d2 gnd can be > 80 ma load at touchscreen and gpio drive ground d1 scl -4 ma i 2 c clock (fail safe, tolerant to 3.6 v regardless of v cc ) c1 sda -4 ma i 2 c data (fail safe, tolerant to 3.6 v regardless of v cc ) b1 p3 +8 ma/-12 ma at 3.3 v gpio-3 / int (3.6 v tolerant within v cc valid range) a1 p2 +8 ma/-12 ma at 3.3 v gpio-2 / reset (3.6 v tolerant within v cc valid range) !-6 x+ (a3) vcc (a2) p2 (a1) y+ (b3) p0 (b2) p3 (b1) x- (c3) p1 (c2) sda (c1) y- (d3) gnd (d2) scl (d1)
STMPE812 functional overview STMPE812 6/49 doc id 17732 rev 1 note: all i/o operates on v cc . all i/o tolerant up to 3.6 v, across v cc = 1.65 - 3.6 v. 8 kv hbm esd on all touchscreen pins (+/- 8 kv vs gnd). 0.5 a max input leakage as input, across v cc range (gpio, scl/sda). 4 s hardware filter on the 4 gpios as input. 1.2 typical application figure 3. typical application b2 p0 +8 ma/-12 ma at 3.3 v gpio-1 / adc ((v in must be less than v cc ) a2 v cc can be > 80 ma load at touchscreen and gpio drive 1.65 - 3.6 v core/io supply (0.1 f decoupling cap) no low-voltage detection for por 20 s por from power stable a3 x+ 50 ma current limit x+ table 2. pin assignments (continued) pin name current capacity function !-6 34-0% ).40 3#, 3$! 6## wire resistive touchscreen 2%3%4 0 '.$ 0 0 #anbeusedas!$# 07-or'0)/ 6
STMPE812 i2c interface doc id 17732 rev 1 7/49 2 i 2 c interface for the bus master to communicate to the slave device, the bus master must initiate a start condition and be followed by the slave device address. accompanying the slave device adress, there is a read/write bit (r/w). the bit is set to 1 for read and 0 for write operation. if a match occurs on the slave device address, the corresponding device gives an acknowledge on the sda during the 9th bit time. if there is no match, it deselects itself from the bus by not responding to the transaction. figure 4. i 2 c timing diagram table 3. i 2 c timing symbol parameter min typ max uni f scl scl clock frequency 0 ? 400 khz t low clock low period 1.3 ? ? s t high clock high period 600 ? ? ns t f sda and scl fall time ? ? 300 ns t hd:sta start condition hold time (after this period the first clock is generated) 600 ? ? ns t su:sta start condition setup time (only relevant for a repeated start period) 600 ? ? ns t su:dat data setup time 100 ? ? ns t hd:dat data hold time 0 ? ? s t su:sto stop condition setup time 600 ? ? ns t buf time the bus must be free before a new transmission can start 1.3 ? ? s ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
i2c interface STMPE812 8/49 doc id 17732 rev 1 2.1 i 2 c features the features that are supported by the i 2 c interface are listed below: i 2 c slave device operates at v cc (1.65 v - 3.6 v) compliant to philips i 2 c specification version 2.1 supports standard (up to 100 kbps) and fast (up to 400 kbps) modes i2c address in 0x41 (0x82/83 including rd/wr bit) start condition a start condition is iden tified by a falling edge of sdata while sclk is stable at high state. a start condition must precede any data/command transfer. the device continuously monitors for a start condition and does not respond to any transaction unless one is encountered. stop condition a stop condition is identified by a rising edge of sdata while sclk is stable at high state. a stop condition terminates communication between the slave device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the slave device into idle mode. when the slave device is in idle mode, it is ready to receive the next i 2 c transaction. a stop condition at the end of a write command stops the write operation to registers. acknowledge bit the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sdata after sending eight bits of data. during the ninth bit, the receiver pulls the sdata low to acknowledge the receipt of the eight bits of data. the receiver may leave the sdata in high state if it does not acknowledge the receipt of the data. 2.2 data input the device samples the data input on sdata on the rising edge of the sclk. the sdata signal must be stable during the rising edge of sclk and the sdata signal must change only when sclk is driven low. table 4. operating modes mode byte programming sequence read 1 start, device address, r/w = 0, register address to be read restart, device address, r/w = 1, data read, stop if no stop is issued, the data read can be continuously performed. if the register address falls within t he range that allows an address auto- increment, then the register addres s auto-increments internally after every byte of data being read. for register address that falls within a non-incremental address range, the ad dress is kept static throughout the entire read operations. refer to the memory map table for the address ranges that are auto and non-increment.
STMPE812 i2c interface doc id 17732 rev 1 9/49 figure 5. read and write modes (random and sequential) write 1 start, device address, r/w = 0, register address to be written, data write, stop if no stop is issued, the data writ e can be continuously performed. if the register address falls within the range that allows address auto- increment, then the register addres s auto-increments internally after every byte of data being written in. for those register addresses that fall within a non-incremental address range, the address is kept static throughout the entire write operation. refer to the memory map table for the address ranges that are auto and non-increment. table 4. operating modes mode byte programming sequence am04175v1 start r/w=0 ack device address reg address ack device address ack r/w=1 data read no ack stop one byte read start r/w=0 ack device address reg address ack restart device address ack r/w=1 data read ack more than one byte read ack no ack stop data read + 1 data read + 2 start r/w=0 ack device address reg address ack data to be written ack stop one byte write more than one byte read start r/w=0 ack device address reg address ack data to write ack stop data to write + 2 ack ack data to write + 1 master slave
i2c interface STMPE812 10/49 doc id 17732 rev 1 2.3 read operation a write is first performed to load the register address into the address counter but without sending a stop condition. then, the bus master sends a restart condition and repeats the device address with the r/w bit set to 1. the slave device acknowledges and outputs the content of the addressed byte. if no additional data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a stop condition. if the bus master acknowledges the data byte, then it can continue to perform the data reading. to terminate the stream of data bytes, the bus master must not acknowledge the last output byte, and be followed by a stop condition. if the address of the register written into the address counter falls within the range of addresses that has the auto-increment function, the data being read comes from consecutive addresses, which the internal address counter automatically increments after each byte output. after the last memory address, the address counter 'rolls-over' and the device continues to output data from the memory address of 0x00. similarly, for the regi ster address that falls within a non-increment range of addresses, the output data byte comes from the same address (which is the address referred by the address counter). acknowledgement in read operation for the above read command, the slave device waits, after each byte read, for an acknowledgement during the ninth bit time. if the bus master does not drive the sda to a low state, then the slave device terminates and switches back to its idle mode, waiting for the next command. 2.4 write operations a write is first performed to load the register address into the address counter without sending a stop condition. after the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (referred by the address counter). the slave device again acknowledges and the bus master terminates the transfer with a stop condition. if the bus master needs to write more data, it can continue the write operation without issuing the stop condition. whether the address counter autoincrements or not after each data byte write depends on the address of the register written into the address counter. after the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminate the write operation by sending a stop condition. when the address counter reaches the last memory address, it 'rolls-over' to the next data byte write.
STMPE812 power supply doc id 17732 rev 1 11/49 3 power supply the STMPE812 gpio operates from a supply pin v cc . for better resolution and noise immunity, v cc above 2.8 v is recommended. power up reset the STMPE812 is equipped with an internal por circuit that holds the device in reset state, until the v cc supply input is valid. the internal por is tied to the v cc supply pin.
charge pump STMPE812 12/49 doc id 17732 rev 1 4 charge pump the STMPE812 is integrated with an internal charge-pump. the charge pump is required for any adc/tsc operations when v cc is less than 2.5 v. activating the charge pump when v cc > 2.5 v may result in permanent damage of the device.
STMPE812 power modes doc id 17732 rev 1 13/49 5 power modes the STMPE812 operates in a 2 states: active and hibernate. active: ? whenever pen-down is detected, the device remains in active mode ? whenever pwm is active, the device remains in active mode ? whenever adc is active, the device remains in active mode hibernate: -pwm/adc must be ?off? (clock disable bit set) -any gpio input, with interrupt enabled cause a transition to ?active? state, if an input change is detected. -pen down even causes transition to ?active? state if the touchscreen controller is enabled. table 5. power mode power mode active hibernate current consumption 280 a (max) (1) 1. at vcc=1.8v, tcs running at 100set s of x/y per second, mav disabled. 1.0 a (max.) gpio hotkey yes yes touchscreen yes yes interface (i 2 c) yes yes
power modes STMPE812 14/49 doc id 17732 rev 1 figure 6. power modes state diagram on power up reset, the device goes to active state. however, as all the functional blocks are clocked off by default, no touch/hotkey activity is possible. if there are no i 2 c activities, device goes into auto-hibernate mode automatically. the auto-hibernate feature of STMPE812 is always enabled. whenever there is a period of inactivity, the device enters this mode to r educe power consumption. on detection a touch, correctly addressed i 2 c data, gpio activity, the device wakes up immediately. as the device is able to wake up very quickly, there is no loss of touch data. !-6 !#4)6% !54/ ()"%2.!4% )#activity 4ou ch(otkey .oactivity ms 0/2 3oft 2eset2esetinput 2eset)nput 34-0%isin activemodeif07- isrunning
STMPE812 STMPE812 registers doc id 17732 rev 1 15/49 6 STMPE812 registers this section lists and describes the registers of the STMPE812 device, starting with a register map and then provides detailed descriptions of register types. table 6. register summary map table address register name bit type reset value function registers from 0x00 - 0x0f are always accessible. 0x00 - 01 chip_id 16 r 0x0812 device identification 0x02 id_ver 8 r 0x10 revision number 0x10 for engineering sample 0x03 sys_ctrl 8 r/w 0x0f system control register 0x04 port_functi on 8 r/w 0x00 port function control register 0x06 - 07 scratch_pad 16 r/w 0x00 general purpose storage register 0x08 int_ctrl 8 r/w 0x00 interrupt control register 0x09 int_en 8 r/w 0x00 interrupt enable register 0x0a int_sta 8 r 0x00 interrupt status register registers from 0x10 - 0x1f are accessible only if ?gpio_off? bit in sys_ctrl is set to ?0?. 0x10 gpio_set_pin 8 r/w 0x00 gpio set pin register 0x11 gpio_clr_pin 8 r/w 0x00 gpio clear pin register 0x12 gpio_mp_sta 8 r/w 0x00 gpio monitor pin state register 0x13 gpio_dir 8 r/w 0x00 gpio falling edge register 0x14 gpio_ed 8 r/w 0x00 gpio rising edge register registers from 0x20 - 0x2f are accessible only if ?adc_off? bit in sys_ctrl is set to ?0?. 0x20 adc_ctrl 8 r/w 0x32 adc control 0x21 - 22 adc_data 16 r 0x0000 adc data registers from 0x40 - 0x4f are accessible only if ?tsc_off? bit in sy s_ctrl is set to ?0?. 0x40 tsc_ctrl 8 r/w 0x00 4-wire touchscreen controller setup 0x41 tsc_det_cfg 1 8r/w 0xa4 touchscreen controller configuration 1 0x42 tsc_det_cfg 2 8r/w 0xb0 touchscreen controller configuration 2 0x43 tsc_samplin g_rate 8r/w 0x0a touchscreen controller sampling rate register
STMPE812 registers STMPE812 16/49 doc id 17732 rev 1 6.1 auto-increment/non auto-increment address the STMPE812 supports auto-increment accesses on all, except for tsc data register (0x44). while accessing auto-increment register location, consecutive read/write access data from the consecutive registers. note that for register accesses started on auto- incremental addresses, the address 0x44 is skipped. for example: write register address (0x40) read data (data of 0x40) read data (data of 0x41) read data (data of 0x42) read data (data of 0x43) read data (data of 0x45) <= 0x44 is skipped. 0x44 tsc_data 8 r - non auto-increment address registers from 0x50 - 0x5f are accessible only if ?pwm_off? bit in sys_ctrl is set to ?0?. 0x50 pwm_clock_ div 8 r/w 0x00 pwm clock divider 0x51 pwm_ctrl1 8 r/w 0x00 master control of pwm channel 1 table 6. register summary map table (continued) address register name bit type reset value function
STMPE812 system and identification registers doc id 17732 rev 1 17/49 7 system and identification registers sys_ctrl system control register address: 0x03 type: r/w reset: 0x0f description: system control register. if the clock supply to a particular functional block is turned off, the registers of these modules are not accessible. table 7. system and identification registers map address register name bit type reset function 0x00 - 01 chip_id 16 r 0x0812 device identification 0x02 id_ver 8 r 0x10 revision number 0x10 for engineering sample 0x03 sys_ctrl 8 r/w 0x0f system control register 0x04 port_function 8 r/w 0x00 port function control register 0x06 - 07 scratch_pad 16 r/w 0x00 general purpose storage register 7 6 543 2 1 0 reserved soft_reset tsc_en reserved pwm_off gpio_off tsc_off adc_off 0 0 001 1 1 1 [7] reserved [6] soft_reset reset the 812 using serial communication all register values are resetted. state machines all back to por states. [5] tsc_en write ?1? to enable operation of tsc. write ?0? to disable it. [4] reserved [3] pwm_off writing ?1? switches off the clock supply to pwm [2] gpio_off writing ?1? switches off the clock supply to gpio [1] tsc_off writing ?1? switches off the clock supply to touchscreen controller [0] adc_off writing ?1? switches off the clock supply to adc
system and identification registers STMPE812 18/49 doc id 17732 rev 1 port_function port funct ion control register address: 0x04 type: r/w reset: 0x00 description: port function control register. port function: '00' - gpio input '01' - gpio output '10' - adc input (p0/p1 only) '11' - special function special function for: p0 - none p1 - pwm p2 - reset input (low pulse > 4 s triggers a hard-reset) p3 - int output scratch_pad scratch pad register address: 0x06 - 07 type: r/w reset: 0x00 description: general purpose scratch pad register. could be used for testing of serial interface reliability. 76543 2 1 0 port 3 function port 2 functio n port 1 function port 0 function 00000 0 0 0 [7:6] port 3 function [5:4] port 2 function [3:2] port 1 function [1:0] port 0 function 76543 2 1 0 scratchpad 00000 0 0 0 [15:0] scratchpad
STMPE812 interrupt system doc id 17732 rev 1 19/49 8 interrupt system the STMPE812 uses a 2-tier interrupt structure. in normal mode, interrupts from the gpio and touchscreen controller assert the int pin and are available in the interrupt status register (isr). in pen down mode, the int pin is asserted as long as pen down is detected. figure 7. interrupt system diagram !-6 ) nterrupt enable )nterrupt status !.$ ).4pin /2 !.$ 0%.$/7.-/$% 0%.$/7. 4ouchscreenstatus 07-'0)/activity
interrupt system STMPE812 20/49 doc id 17732 rev 1 int_ctrl interrupt control register address: 0x08 type: r/w reset: 0x00 description: this register is used to enable the interruption from a system related interrupt source to the host. 76543 2 1 0 int_mode reserved int_polarity int_type global_int 00 000 [7] int_mode: ?0? for pen-down int mode (int pin asserted as long as pen down detected). nothing can de- assert the int pin as long as pen is down. tsc_touch in int_en register must be enabled for pen_down interrupt to operate. if any other interrupt sources are enabled, the int output is: pen_status or other_int int_e setting is not required for pen-down mode. ?1? for normal int mode (int pin asserted if any bit in int status register is set) when int_mode is changed, all interrupt status are cleared. pending int output (if any) is cleared too. [6:3] reserved [2] int_ polarity: ?1? for active high/rising edge ?0? for active low/falling edge interrupt pin should be pulled to v cc if ?active low? polarity is used, and pulled to gnd if ?active high? polarity is used. [1] int_type: ?1? for edge interrupt (pulse width = 50-150 s) ?0? for level interrupt edge interrupt does not work in pen_down int mode this bit is ignored in pen_down int mode. [0] global_int: ?1? allows global interrupt ?0? stops all interrupt this bit overwrites int_mode: if global_int is stop (in pen down int_mode), even pen down does not generate an interrupt.
STMPE812 interrupt system doc id 17732 rev 1 21/49 int_en interrupt enable register address: 0x09 type: r/w reset: 0x00 description: this register is used to enable the interruption from a system related interrupt source to the host. note: hotkey interrupt should have respond time of <5 s in active mode and less than 1 ms in hibernate mode. 76543 2 1 0 tsc_err tsc_release p3 p2 p1 p0 tsc_data tsc_touch 00000 0 0 0 [7] tsc_err error encountered in coordinate calculation in touchscreen controller [6] tsc_release: release of tsc is detected [5] p3 port 3 activity (gpio) [4] p2 port 2 activity (gpio) [3] p1 port 1 activity (gpio/adc/pwm) [2] p0 port 0 activity (gpio/adc) [1] tsc_data touch data available [0] tsc_touch touch is detected
interrupt system STMPE812 22/49 doc id 17732 rev 1 isr interrupt st atus register address: 0x0a type: r reset: 0x00 description: isr register monitors the status of the interruption from a particular interrupt source to the host. regardless whether the int_en bits are enabled, the isr bits are still updated. writing to this register has no effect. reading the register clears any asserted bit implementation: a shadow register must be used to ensure that read+clear action does not clear up any bit that is not read. note: reading the interrupt enable register also clears the isr. it is recommended that no read operation on ier to be executed during normal operation. ier should only be accessed during initialization. in pen_down interrupt mode, this status regist er is still updated with event interrupt status data, and cleared on read. however no interrupt is issued based on this status register. 7 6 543 2 1 0 tsc_err tsc_release p3 p2 p1 p0 tsc_data tsc_touch 0 0 000 0 0 0 [7] tsc_err error encountered in coordinate calculation in tsc, or touch detect not valid after sampling [6] tsc_release: release of touch is detected [5] p3 port 3 activity (gpio) [4] p2 port 2 activity (gpio) [3] p1 port 1 activity (gpio/adc/pwm) [2] p0 port 0 activity (gpio/adc) [1] tsc_data touch data available. in internal timer and host-read controlled mode, this bit can only be cleared after the data has been read by the host. in acq mode, this bit is cleared when host reads the isr. [0] tsc_touch touch is detected. (in pen-down interrupt mode, this bit is never cleared until pen is removed)
STMPE812 adc controller doc id 17732 rev 1 23/49 9 adc controller a 12-bit adc is integrated in the STMPE812. the adc could be used as generic analog- digital converter, or a touchscreen controlle r capable of controlling a 4-wire resistive touchscreen. the adc works only with internal reference (equal to v cc ) , always 12 bit. table 8. address register name bit type reset description 0x20 adc control 8 r/w 0x32 adc control 0x21-0x22 adc data 16 r 0x0000 adc data access (p0/p1)
adc controller STMPE812 24/49 doc id 17732 rev 1 adc control regi ster adc control address: 0x20 type: r/w reset: 0x32 description: this register is used to configure the adc operations. 76543 2 1 0 adc_mode adc_cap adc_freq cp_arm cp_lock[1:0] adc_port 00110 0 1 0 [7] adc_mode: adc capture mode ?0? ? continuous capture according to sampling rate specified by adc_freq register. new data over-writes old data in adc_data register. ?1? ? one-shot capture. one sample is taken every time system writes ?1? to adc_cap bit [6] adc_cap: adc channel data capture in one-shot mode: write ?1? to initiate data acquisition for th e corresponding channel. writing ?0? has no effect. reads ?1? if conversion is in progress.reads ?0? if conversion is completed. one-shot mode adc generates interrupt in co rresponding interrupt status bit on completion of conversion in continuous capture mode: write ?1? to initiate data acquisition for the corresponding channel. writing ?0? to stop capturing. [5:4] adc_freq: adc sampling frequency based on 1mhz rc (minimum 880 khz) 00 ? 10 k samples/sec 01 ? 12.5 k samples/sec 10 ? 15 k samples/sec 11 ? 20 k samples/sec note: as the adc is also used for tsc operation. this setting affects the maximum sampling rate possible with tsc. [3] cp_arm: writing ?1? arms the charge-pump for unlocking writing ?0? un-arms it charge-pump is required for adc/tsc operation when vcc is less than 2.5v. activating the charge pump when vcc is mo re than 2.5v may result in permanent damage of the device. charge-pump can be activated by unlocking cp_lock after it is armed. [2:1] cp_lock[1:0]: only effective if cp_arm is set to ?1?. always reads ?00?. writing ?01? when cp_arm is ?1? activates the charge pump. writing ?00?, ?10? and ?11? does not activate the charge-pump, and clears the cp_arm bit. cp_arm must be set before writing to cp_lock. accesses to cp_lock is ignored, if cp_arm is ?0?. note: note: cp_arm and cp_lock cannot be accessed in a single i 2 c transaction. system must first arm the cp with 1 i 2 c transaction, and unlocks it in the next. cp_lock reads ?00? if ch arge pump is activated cp_lock reads ?01? if char ge pump is not activated
STMPE812 adc controller doc id 17732 rev 1 25/49 adc data adc data register address: 0x21-0x22 type: r reset: 0x0000 address: adc data register. note: when the i 2 c master accesses the data register, upper/lower byte consistency must be guaranteed (once access starts, content is updated only after both bytes has been read, or i 2 c master accesses other register address): - 0x21 is lsb - 0x22 is msb [0] adc_port: selects one of the port as adc input. 00- port 0 01- port 1 76543 2 1 0 adc_data_7 adc_data_6 adc_data_5 adc_data_4 adc_data_3 adc_data_2 adc_data_1 adc_data_0 00000 0 0 0 [7:0] adc_datax
pwm controller STMPE812 26/49 doc id 17732 rev 1 10 pwm controller the pwm allows the brightness control of a led/motor driver. the pwm uses base clock that is ? of the osc frequency (typically 600 khz). the base clock is divided by a programmable div[4:0], which scales it to 18.75-600 khz. this clock goes into pwm controller and outputs a signal that is pulse-width modulated (16 steps), with a frequency 16 times smaller. 10.1 register map for pwm function table 9. pwm function registers pwm clock div register pw m clock divider register address: 0x50 type: r/w reset: 0x00 description: pwm clock divider register. address register name bit type reset description 0x50 pwm_clockdiv 8 r/w 0x00 pwm clock divider 0x51 pwm_control_1 8 r/w 0x00 master control of pwm channel 1 output at port 0 76543 2 1 0 burstlength [1:0] div[4:0] 00000 0 0 0 [7:5] burstlength[2:0] burst length of pwm output ?000? ? 8 ms ?001? ? 16 ms ?010? ? 32 ms ?011? ? 64 ms ?100? ? 128 ms ?101? ? 256 ms ?110? ? 512 ms ?111? ? 1024 ms [4:0] div[4:0] pwm controller is based on 600 khz clock divided by ( div[4:0] + 1 ). effectively, pwm clock is: 600 kkz (msx.) 600 khz/32 = 18.75 khz (min.)
STMPE812 pwm controller doc id 17732 rev 1 27/49 pwm control1 register pwm control1 register address: 0x51 type: r/w reset: 0x00 description: pwm control1 register. 76543 2 1 0 brightness burstmultiplier off_state enable 0000 [7:4] this defines the of the pwm channel output whic h in turn determines the brightness level of the led that the pwm output drives. note that this is assuming led is connected in sinking mode. system host should progra m the brightness in a reverse way if sourcing configuration were to be used. 0000: duty cycle ratio 1:15 ( 6.25%, minimum brightness) 0001: duty cycle ratio 2:14 ( 12.50%) 0010: duty cycle ratio 3:13 ( 18.75%) 0011: duty cycle ratio 4:12 ( 25.00%) 0100: duty cycle ratio 5:11 ( 31.25%) 0101: duty cycle ratio 6:10 ( 37.50%) 0110: duty cycle ratio 7: 9 ( 43.75%) 0111: duty cycle ratio 8: 8 ( 50.00%) 1000: duty cycle ratio 9: 7 ( 56.25%) 1001: duty cycle ratio 10: 6 ( 62.50%) 1010: duty cycle ratio 11: 5 ( 68.75%) 1011: duty cycle ratio 12: 4 ( 75.00%) 1100: duty cycle ratio 13: 3 ( 81.25%) 1101: duty cycle ratio 14: 2 ( 87.50%) 1110: duty cycle ratio 15: 1 ( 93.75%) 1111: duty cycle ratio 16: 0 (100.00%, maximum brightness) [3:2] burstmultiplier pwm output continues for time = burstlength * burstmultiplier *if burstmultiplier = 0, pwm output i ndefinitely (until pwm is turned off) 1 off_state ?0? : pwm output ?hi? when pwm not running ?1? : pwm output ?low? when pwm not running 0enable writing ?1? to this bit starts the pwm controller sequence writing ?0? has stops it reads ?1? when pwm is running.
pwm controller STMPE812 28/49 doc id 17732 rev 1 10.2 interrupt of pwm controller when non-infinite sequence is used, the completion of pwm sequence causes the p0 bit in interrupt status register to be asserted.
STMPE812 touchscreen controller doc id 17732 rev 1 29/49 11 touchscreen controller the STMPE812 is integrated with a hard-wired touchscreen controller for 4-wire resistive type touchscreen. the touchscreen controller is able to operate completely autonomously, and would interrupt the connected cpu only when pre-defined event occurs. the tsc is based on an internal 20ksamples/sec adc, running off a 1 mhz (minimum 880 khz) rc osc. sampling time = touch detect delay*2 + (sett ling time + (adc conversion time*mav ) ) *3 figure 8. touchscreen controller internal rc osc connection table 10. sampling time/frequency calculation oscillator speed adc conversion time touch detect delay settling time median averag e sampling time/freq (complete x/y/z sample sets) 880khz 50s 40s 40s none 40*2 + 3*(40+(50*1)) = 350 s (2.8k sample sets/sec) 880khz 50s 40s 40s 10-2 40*2 + 3*(40+ (50*10))=1700 s (588 sample sets/sec) 880 khz 50 s 640 s 640 s 20-4 640*2 + 3*(640+ (50*20)) =6200 s (161 sample sets/sec) !-6 -(z minimum+ 2#/3# bit ch!$# max +samplessat-(z 43#timinggenerator 43#samplingrate ms ms
touchscreen controller STMPE812 30/49 doc id 17732 rev 1 11.1 touchscreen contro ller detection sequence following is the sequence of detection in the STMPE812 touchscreen controller for x, y and z: 1. touch detect 2. drive y 3. wait for settling time 4. measure y 5. stop drive 6. drive z 7. wait for settling time 8. measure z 9. stop drive 10. drive x 11. wait for settling time 12. measure x 13. stop drive 14. touch detect 11.2 3 modes of acquisition 1. data acquisition timed by internal timer: the host system selects a ?sampling period? with, based on internal timer, the touchscreen controller takes a comple te set of samples on every period. the host system may choose to read the data by: ? waiting for the int ? polling for int_status register for touch data ? reading the tsc_data at approximately the same timing. (use ?status read? option in this mode) 2. data acquisition triggered by a write to ?acq? bit: as and when sampling is desired, host writes to the acq bit and: ? poll the acq to wait for completion ? wait for int for touch data access ? poll the fifo after approximate time required for sampling. (use ?status read? option in this mode) 3. data acquisition using host-c ontrolled sampling rate control the host sets the internal timer for the desired data-rate. on staring the touchscreen controller in this mode, a complete set of sample is taken immediately. the touchscreen controller enters in hibernate mode (clock is turned off, only monitors the pen-down status). when system host reads the touch data available in fifo, another set of data is taken immediately.
STMPE812 touchscreen controller doc id 17732 rev 1 31/49 11.3 touchscreen co ntroller registers table 11. touchscreen controller registers address register name bit type reset function 0x40 tsc_ctrl 8 r/w 0x00 touchscreen control 0x41 tsc_det_cfg1 8 r/w 0xa4 touchscreen detection config 1 0x42 tsc_det_cfg2 8 r/w 0xb0 touchscreen detection config 2 0x43 tsc_sampling _rate 8 r/w 0x0a touchscreen sampling rate 0x44 tsc_data 8 r ? touchscreen data
touchscreen controller STMPE812 32/49 doc id 17732 rev 1 tsc ctrl tsc control register address: 0x40 type: r/w reset: 0x00 description: touchscreen control register. 76543 2 1 0 mav_mode[2:0] acq precharge[1:0] current limit [1:0] 000 0 [7:5] mav_mode[2:0] ?000? ? mav filter disabled ?001? ? 6 remove 2 ?010? ? 8 remove 4 ?011? ? 10 remove 2 ?100? ? 12 remove 4 ?101? ? 20 remove 4 ?110? ? 4 remove none (equal to 4x oversampling) ?111? ? 8 remove none (equal to 8x oversampling) [4] acq only valid in acquisition mode ?01? (acquisition initiated by system host writing to acq bit) writing ?1? to this bit initiates a tsc data acquisition writing ?0? has no effect reads ?1? if data acquisition is in progress reads ?0? if data is ready if data is already available in buffer and not read by system host, setting this bit to ?1? renders the data in buffer ?invalid?. data available bit in interrupt status register is reset by hardware automatically. pending interrupt due to data available (if any) is cleared. data pointer in multi-byte read operation is resetted when this bit is written to. [3:2] precharge[1:0] pre-charge driver for touch detection ?00? ? no pre-charge ?01? ? 2 s pre-charge ?10? ? 4 s pre-charge ?11? ? 8 s pre-charge [1:0] current limit [1:0] current limit of touchscreen driver ?00? ? 5 ma ?01? ? 10 ma ?10? ? 20 ma ?11? ? 30 ma
STMPE812 touchscreen controller doc id 17732 rev 1 33/49 tsc detect config tsc detecti on configuration 1 register address: 0x41 type: r/w reset: 0xa4 description: touchscreen controller detection configuration 1 register. 76543 2 1 0 penstrength[1:0] tdetdly[2:0] settling[2:0] 10100 1 0 0 [7:6] penstrength[1:0] pen detect strength threshold ?00? ? least sensitive (50 k pull-up) ?01? ? sensitive (40 k pull-up) ?10? ? more sensitive (30 k pull-up) - default ?11? ? most sensitive (20 k pull-up) [5:3] tdetdly[2:0] touch detect delay ?000? = 40 s ?001? = 80 s ?010? = 160 s ?011? = 320 s ?100? = 640 s - default ?101? = 1.28 ms ?110? = 2.56 ms ?111? = 5.12 ms [2:0] settling[2:0] panel driver settling time ?000? = 40 s ?001? = 80 s ?010? = 160 s ?011? = 320 s/ns ?100? = 640 s - default ?101? = 1.28 ms ?110? = 2.56 ms ?111? = 5.12 ms for large panels (> 6 inches), a capacitor of 10 nf is recommended at the touchscreen terminals for noise filtering. in this case, settling time of 1 ms or more is recommended.
touchscreen controller STMPE812 34/49 doc id 17732 rev 1 tsc_det_cfg2 tsc detection configuration 2 register address: 0x42 type: r/w reset: 0xb0 description: touchscreen controller detection configuration 2 register. 76543 2 1 0 acq_mode statusread opmode z-divider[3:0] 10110 0 0 0 [7:6] acq_mode ?00? ? data acquisition timed by internal timer ?01? ? data acquisition triggered by a write to ?acq? bit ?10? ? data acquisition using host-controlled sampling rate control. (default) ?11? ? reserved in mode ?10?, device sample a complete data set every time host accesses the buffer. after completion of sampling, device enters hibernate mode, until data is accessed again. (or pen- up causing interrupt to de-assert) [5] statusread ?1? inserts interrupt status read in data port. (default) reading data port in this mode clears interrupt st atus (equivalent to accessing interrupt status register) ?0? ? no interrupt status access by data port [4] opmode tsc operating mode ?0? for 12-bit x,12-bit y,8-bit z acquisition ?1? for 12-bit x, 12-bit y only (default) this field cannot be written on, when en=1 [3:0] z-divider[3:0] pen-pressure is internally calculated as a 16-bit integer. as 16-bit resolution is typically not required for touchscreen operation, STMPE812 right-shifts the value internally by z- divider[3:0]. z-value read through the tsc data register is the lowest 8-bit of the shifted value.
STMPE812 touchscreen controller doc id 17732 rev 1 35/49 tsc sampling rate tsc sam pling rate register address: 0x43 type: r/w reset: 0x0a description: touchscreen controller sampling rate control register. tsc_data touchscreen data register address: 0x42 type: r/w reset: 0xb0 description: the data format of the touchscreen scontroller data register depends on the setting of ?opmode? field in the touchscreen detection configuration 2 register. the samples acquired are accessed in ?packed samples?. the size of each ?packed sample? depends on which mode the touchscreen controller is operating in. note: it is extremely important for system host to read exactly the number of bytes in each operating mode, to preserve the integrity of data stored. note: data pointer in this 1-level buffer could be reset by: -user issued acq in user initiated acquisiti on mode. in mode ?10?, every time sampling is completed, it overwrites the buffer, and reset the data pointer 76543 2 1 0 sampling 00001 0 1 0 [7:0] sampling[7:0] sets the sampling rate of touchscreen controller. sampling time = (sampling[7:0]+1) in ms clock cycle = 1 s (1 mhz rc osc) sampling time = 1 ms ? 256 ms note: this is used as ?tsc regular initiator signal?. as long as there remains a valid touch, every interval of this timing, the touchscreen contro ller executes a complete drive/settling/multi- sample/mav/data calculation. it is the user?s re sponsibility to choose a sampling time that is enough, based on adc_freq, settling time and filter. 76543 2 1 0 tsc_data_7 tsc_data_6 tsc_data_5 tsc_data_4 tsc_data_3 tsc_data_2 tsc_data_1 tsc_data_0 00000 0 0 0 [7:0] tsc_data_x: data byte from touchscreen controller.
touchscreen controller STMPE812 36/49 doc id 17732 rev 1 table 12. touchscreen controller data register tscdetectconfig2 number of bytes to read from tscdata byte0 byte1 byte2 byte3 byte4 opmode statusread 0 0 4 [11:4] of x [3:0] of x [11:8] of y [7:0] of y [7:0] of z 1 0 3 [11:4] of x [3:0] of x [11:8] of y [7:0] of y - 01 5 interrupt status [11:4] of x [3:0] of x [11:8] of y [7:0] of y [7:0] of z 11 4 interrupt status [11:4] of x [3:0] of x [11:8] of y [7:0] of y -
STMPE812 touchscreen controller doc id 17732 rev 1 37/49 11.4 programming model below are steps to configure the touchscreen controller in 3 different acquisition modes. a. 811-style touchscreen controller, 100 hz, lowest power possible 1. initialize the touchscreen controller (choose acq_mode ?00? - data acquisition timed by internal timer) 2. initialize interrupt (with tsc_data enabled, normal interrupt mode) 3. wait for interrupt 4. on interrupt: read interrupt status (this clears the set bits too) 5. if data is available, read data. note: if one set of data is available in buffer, and not accessed by the i 2 c host, yet the sampling timer is up for the next data, the STMPE812 samples the next data as scheduled. if old data is still not accessed when new data is ready to be written to the buffer, it is over- written. if old data is in progress of bein g accessed, new data is discarded. if i 2 c host accessed part of the data, and moved on to read any other register location, the existing data is considered r ead, and new data ready to be written into buffer b. non-autonomous touchscreen controller style-interrupt, 100hz, lowest power possible: 1. initialize tsc (choose acq_mode ?01? - data acquisition triggered by a write to ?acq? bit) 2. initialize interrupt (wit h tsc_data, tsc_touch enabled, pen_down interrupt mode) 3. wait for interrupt 4. on interrupt: read interrupt status (this clears the set bits too) 5. if pen_down, start syst em_timer (10 ms typically) 6. on timeout, write acq bit to start acquisition 7. poll interrupt status register or acq bit to check for acquisition status 8. on issuing acq, 812 may assume that data in buffer is already accessed by i2c host, and reset the relevant pointers. c. host-controlled sampling rate (lowest bus utilization) 1. initialize tsc (choose acq_mode ?10? - data acquisition us ing host-controlled sampling rate control) 2. initialize interrupt (wit h tsc_data, tsc_touch enabled, pen_down interrupt mode) 3. wait for interrupt 4. on interrupt: read interrupt status (this clears the set bits too) 5. if pen_down, start syst em_timer (10 ms typically) 6. on timeout, read data
touchscreen controller STMPE812 38/49 doc id 17732 rev 1 the STMPE812 samples a new data set immediately after every complete read. if the host does not complete a data-set read, no further samples are taken. for each data point (4 bytes), number of i 2 c transaction required is: a: read int_sts (1 byte), read data (4 bytes) b: write acq (1 byte), read acq (1 byte), read data (4 bytes) c: read (4 bytes)
STMPE812 gpio port controller doc id 17732 rev 1 39/49 12 gpio port controller a total of 4/6 configurable ports are available in the STMPE812 port expander device. if configured as gpio input/output, they are controlled by the gpio registers. all gpio registers are named as gpxx, where: xxx represents the functional group the function of each bit is shown in ta bl e 1 4 : if both gpfe and gpre are not set, state transition on a gpio does not cause an interrupt. on power-up reset, all gpio are set as input. table 13. gpio registers address register bit type reset function 0x10 gpio_set_pin 8 r/w 0x00 set pin state 0x11 gpio_clr_pin 8 r/w 0x00 clear pin state 0x12 gpio_mp_sta 8 r/w 0x00 monitor pin state 0x13 gpio_dir 8 r/w 0x00 falling edge detection enable 0x14 gpio_ed 8 r/w 0x00 rising edge detection enable bit 76543210 gpxx io-3 io-2 io-1 io-0 table 14. gpio registers register name function gpio monitor pin state reading this bit yields the current state of the bit. writing has no effect. gpio set pin state writing ?1? to this bit causes the corresponding gpio to go to ?1? state. writing ?0? to this bit has no effect reading this register always yield 0x00 gpio clear pin state writing ?1? to this bit causes the corresponding gpio to go to ?0? state. writing ?0? to this bit has no effect reading this register always yield 0x00 gpio falling edge detection enable writing ?1? to this bit allows interrupt generation when there is a falling edge at the corresponding gpio writing ?0? disables the interrupt generation on falling edge detection gpio rising edge detection enable writing ?1? to this bit allows interrupt generation when there is a rising edge at the corresponding gpio writing ?0? disables the interrupt generation on rising edge detection
electrical specification STMPE812 40/49 doc id 17732 rev 1 13 electrical specification table 15. absolute maximum rating symbol ratings maximum value unit v cc supply voltage 4.5 v vi-i2c input voltage at sda/scl 4.5 v vi-io input voltage at p0-p5 4.5 v esd on all touchscreen and gpio pins (hbm) 8 kv on all other pins (hbm) 2 kv table 16. thermal data symbol parameter value unit t j thermal resistance junction-ambient (flip-chip12) 68 c / w t operating temperature -40c-85c c t stg storage temparature -65c-125c c table 17. power consumption (t amb = -40 c to 85 c) symbol parameter test conditions min typ max unit v cc core supply voltage 1.65 ? 3.6 v i cc max operating current v cc =1.8v tsc running at 100 sets of x/y per second mav disabled ? 100 120 a vcc=1.8v tsc running at 100 sets of x/y per second mav 6 remove 2 ? 230 280 i cc max operating current v cc =3.3v tsc running at 100 sets of x/y/z per second mav 10 remove 2 ? 670 810 a vcc=1.8 v tsc running at 100 sets of x/y/z per second mav 10 remove 2 ? 470 570
STMPE812 electrical specification doc id 17732 rev 1 41/49 *operating current excludes current driving the touchscreen. 13.1 dc electrical characteristics (-40 c to 85 c . all gpio complies to jedec standard jesd-8-7) 13.2 ac electrical characteristics i cc max operating current v cc =1.8v tsc running at 100 sets of x/y/z per second mav 20 remove 4 ? 870 1050 a i cc max operating current v cc =3.3v tsc running at 100 sets of x/y/z per second mav 20 remove 4 ? 1190 1430 a i cc suspend suspend current no i2c/adc activity v cc = 1.8 v - 3.3 v ?0.5 1a table 17. power consumption (t amb = -40 c to 85 c) (continued) symbol parameter test conditions min typ max unit table 18. dc electrical characteristics symbol parameter test co nditions min typ max unit v il input voltage low state v cc =1.65-3.3v -0.3 ? 0.20 v c c v v ih input voltage high state v cc = 1.65 - 3.3 v 0.80 v cc ?v cc +0.3 v v ol output voltage low state v cc =3.3v, i ol =12ma -0.3 ? 0.45 v v oh output voltage high state v cc =1.65 v, i oh =8 ma 0.85 v cc ?v cc +0.3 v i leakage all input pins except for touchscreen i/o and p0/p1 v cc = 1.65 v, v in 3.6 v ? 0.1 0.5 a table 19. ac electrical characteristics (-40 c to 85 c) symbol parameter test conditions min typ max unit max clki2c i2c maximum sclk v cc =1.8-3.3v ? ? 400 khz maxclki2 c i2c maximum sclk v cc = 1.8 - 3.3 v ? ? 120 khz
electrical specification STMPE812 42/49 doc id 17732 rev 1 tr e s e t minimum reset pulse width 4? ?s tin minimum input width required for gpio state transition 4? ?s f osc internal rc osc frequency v cc = 1.8 v 900 1200 1500 khz f osc internal rc osc frequency v cc = 3.3 v 900 1200 1500 khz table 20. adc sp ecification parameter test conditions min typ max unit full-scale input span 0 ? v cc v absolute input range -0.2 ? v cc +0. 2 v input capacitance ? 25 ? pf leakage current ? 0.1 ? a resolution ? 12 ? bits no missing codes 11 ? ? bits integral linearity error ? 4 ? lsb offset error ? 5 5 lsb gain error ? 14 18 lsb noise including internal vref ?50? uvrms power supply rejection ratio ? 50 ? db throughput rate ? 180 ? ksamples/s table 21. switch drivers specification parameter test conditions min typ max unit on resistance x+, y+ v cc =1.65- 3.6 v ?7 15ohm on resistance x-, y- v cc =1.65- 3.6 v ?7 15ohm drive current (at 5 ma limit) v cc = 1.65 -3.6 v x+/x- or y+/y- shorted together externally ?? 10ma table 19. ac electrical characteristics (-40 c to 85 c) symbol parameter test conditions min typ max unit
STMPE812 electrical specification doc id 17732 rev 1 43/49 drive current (at 10 ma limit) v cc =1.65 -3.6 v x+/x- or y+/y- shorted together externally ?? 20ma drive current (at 20 ma limit) v cc =1.65 -3.6 v x+/x- or y+/y- shorted together externally ?? 40ma drive current (at 30 ma limit) v cc =1.65 -3.6v x+/x- or y+/y- shorted together externally ?? 60ma table 21. switch drivers specification (continued) parameter test conditions min typ max unit
package mechanical section STMPE812 44/49 doc id 17732 rev 1 14 package mechanical section in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 9. package outline for flip-chip 12
STMPE812 package mechanical section doc id 17732 rev 1 45/49 figure 10. footprint recommendation table 22. flip-chip 12 mechanical data symbol millimeters min typ max a 0.60 0.65 0.70 a1 0.22 0.25 0.28 a2 0.33 0.35 0.37 b 0.290 0.315 0.340 d 2.155 2.17 2.185 d1 1.49 1.5 1.51 e 1.655 1.67 1.685 e1 0.99 1.0 1.01 e 0.46 0.5 0.54 fd 0.327 0.335 0.343 fe 0.327 0.335 0.343 sd ? 0.25 ? ccc ? 0.08 ? $ ? 0.05 ?
package mechanical section STMPE812 46/49 doc id 17732 rev 1 figure 11. tape information figure 12. tape orientation u s er direction of feed am00745v1 note: pin a1 is at top left corner based on above tape orientation.
STMPE812 package mechanical section doc id 17732 rev 1 47/49 figure 13. reel information
revision history STMPE812 48/49 doc id 17732 rev 1 15 revision history table 23. document revision history date revision changes 20-jul-2010 1 initial release.
STMPE812 doc id 17732 rev 1 49/49 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STMPE812

	To Download STMPE812 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .